1. Field of the Invention
The present invention relates to a semiconductor memory device having, in addition to a random-access memory (RAM) portion, a shift register for performing parallel data transfer for read/write operations with respect to the RAM portion. The device according to the present invention is directed to ensuring reliable write-in of data into the RAM portion from the shift register without special changes in the RAM portion.
2. Description of the Related Art
A RAM with a shift register which can transfer in parallel the data of one word line of the RAM cell array has been used as a video RAM. In such a RAM device, there are provided a RAM cell array, a shift register, transfer gates controlled by clock signal, bit lines, word lines, sense amplifiers, and dummy cells for data transfer in parallel.
In such a RAM device, when the selection of the word line WL and the opening of the transfer gate are carried out simultaneously, a pair of bit lines simultaneously are given a potential difference by means of the selection of the word line and are given a potential difference by means of the opening of the transfer gate. In this case, there is no particular problem when both work in the same direction (that is, the same polarity), but the cancel each other when they are of opposite polarities. The behavior of the pair of bit lines after the rise of the potential of word line and transfer gate control signal differ depending on the write data and the stored data of the selected cell. Of course, once a write operation is to be carried out, the level definition of bit lines by the data of the shift register must take precedence. For this reason, the capacity of the shift register and dummy cell must be sufficiently large compared to the capacity of both the real cells of the RAM and the dummy cells.
When the potential of the word line is raised simultaneously with a transfer gate control signal, however, the cause of the slight potential difference in the pair of bit lines is not only the output of the shift register and the dummy cell, but also the real cells in the RAM and the dummy cells. Therefore, write-in from the shift register into the real cells cannot be carried out unless the capacity of the output node of the shift register is larger than that of the real cells. To achieve high speed operation of the shift register and low power consumption, it is necessary for the capacity of the output node of the shift register to be smaller. Under these circumstances, it is very difficult to carry out an appropriate writing.
When the voltage difference established for the bit lines by the selected cell and that the data of the shift register are opposite in polarity, for example, if the former lowers the potential of a second bit line and the latter lowers the potential of a first bit line, then both potentials of the first and second bit lines are lowered. Then, because the capacities of the shift register side and dummy cell side increase, even if the function of the former is made relatively weaker, the level drop of the bit lines on the H side is remarkably large, so erroneous writing may occur. In the prior art, a device for enabling more accurate writing from the shift register to the RAM portion has been seeked for.